1. Field of the Invention
The present invention relates to a clock generator for a magnetic disk drive, and more particularly, to a clock generator which is used in a zone-bit-recording type magnetic disk drive and which prevents failure (false) lock (i.e., hangup in phase-lock loops).
2. Description of the Related Art
In the field of magnetic disk drives, recent years have seen increase in the recording density aimed at a reduction in the device size and an increase in the recording capacity, resulting in more intersymbol interference of a read signal. To deal with this, over the past few years, magnetic disks of a partial-response type utilizing intersymbol interference have been brought into practical use. In a partial-response type magnetic disk drive, if a determination point (i.e., sampling point) differs from a signal point of a read signal waveform (i.e., time at which an eye of an eye-pattern opens widest), the error rate increasingly deteriorates. Hence, in order to suppress a timing difference between the signal point and the determination point as much as possible, a clock is reproduced directly from a sampling read signal. The reliability of a clock generator of the magnetic disk drive in recovering the clock timing therefore needs to be improved.
FIG. 1 shows a structure of a clock generator 60 of a conventional magnetic disk drive. A read signal read by a head H from a magnetic disk D in which data are recorded is amplified by an amplifier AP and partially equalized by a partial-response equalizing circuit PE to become an equalized read signal EQ which will be given to a sample-holder circuit 61.
The sample-holder circuit 61 generates a sampling signal Yn from the partially equalized read signal EQ. The sampling signal Yn is given to a partial-response phase-comparison circuit 90 and a data detection part 70. The partial-response phase-comparison circuit 90 comprises a ternary detection circuit 62, a sample-holder circuit 63, a flip-flop 64, multipliers 65 and 66, and a subtracter 67. The sampling signal Yn is supplied to the sample-holder circuit 63 which serves as means for delaying the sampling signal Yn and also to the ternary detection circuit 62.
The ternary detection circuit 62 detects three magnitude values in the sampling signal Yn, i.e., +1, 0 and -1, and generates a detection signal Xn which will be given to the first multiplier 65 and to the flip-flop 64 which serves as means for delaying the detection signal Xn. The sample-holder circuit 63 holds the sampling signal Yn received therein until receipt of a sampling clock so as to generate a delayed sampling signal Yn-1 which is delayed in time by 1 symbol. The flip-flop 64 holds the detection signal Xn received therein until receipt of the same sampling clock signal to thereby generate a delayed detection signal Xn-1 which is delayed in time by 1 symbol.
The delayed sampling signal Yn-1 and the detection signal Xn are fed to the first multiplier 65 where they are multiplied while the sampling signal Yn and the delayed detection signal Xn-1 are given to the second multiplier 66 where they are multiplied. Products calculated at the first and the second multipliers 65 and 66 are given to the subtracter 67 which then calculates the difference between the products given thereto, then the difference is multiplied to thereby detect a phase difference Zn between the sampling clock pulse and the real signal point of the read signal waveform. The phase difference Zn is expressed by the equation below which is described in the literature titled "Timing recovery in digital synchronous receivers" (IEEE TRANSACTION COMMUNICATIONS, VOL. COM-24, No. 5, May 19, p.516-p.531): EQU Zn=-(Yn-1*Xn)+(Yn*Xn-1) (1)
The phase difference Zn is smoothed by a loop filter 68. The phase difference Zn thus smoothed controls the frequency of a voltage-controlled oscillator 69 and the voltage-controlled oscillator 69 outputs a clock signal. The sampling clock timing obtained in this manner is fed back to the sample-holder circuits 61 and 63, the flip-flop 64 and the data detection part 70. Sampling by the sample-holder circuits 61 and 63 and resetting of data by the flip-flop 64 are performed under the control of the same clock timing. At the same time, this clock is given to the data detection part 70 which reproduces data from the sampling signal Yn (e.g., a data detection part for detection data by maximum likelihood detection) and used for reproduction of data.
To increase the speed of recovering this clock timing, in an preamble portion of the data, the following repetition sequences EQU +1, +1, -1, -1, +1, +1, -1, -1 . . .
is written as a training signal and the clock is reproduced at acquisition for clock recovery from the preamble portion as is customarily done. Besides, the data are recorded on the disk D by the zone-bit recording method to enhance the recording density of the data on the disk.
FIG. 2A is a view showing distribution of recording units U in a recording track Tin of an inner periphery of the disk D and a recording track Tout of an outer periphery of the disk D within the conventional zone-bit recording type magnetic disk drive. In the zone-bit recording method, as shown in FIG. 2A, the density of magnetic recording is entirely constant from the inner recording track Tin to the outer recording track Tout and therefore the outer recording track Tout includes the greatest number of the recording units U.
FIG. 2B shows the format of recorded data in each recording unit U of FIG. 2A. Each recording unit U includes a preamble portion in which the training signal is written and a data portion in which the data are recorded.
FIG. 3A is a waveform diagram showing the waveform of the training signal written in the preamble portions of FIG. 2B as it is read at the outer track Tout while FIG. 3B is a waveform diagram showing the waveform of the training signal written in the preamble portions of FIG. 2B as it is read at the inner track Tin. For example, in a case where the number of the recording units U of the outer track Tout is double that of the inner track Tin in FIG. 2A, the frequency of the waveform of the training signal read at the outer track Tout is double that of the training signal read at the inner track Tin.
Assume in FIGS. 3A and 3B that the points indicated at are normal signal points at which the clock signal is hungup and the points indicated at .quadrature. are signal points at which the clock generator is hungup as shown in FIG. 3C, at the outer track Tout, the normal frequency is 4f1 and the hangup frequency is 2f1 while at the inner track Tin, the normal frequency is 2f1 and the hangup frequency is f1.
However, in the conventional clock generator of the conventional zone-bit recording type magnetic disk drive, as shown in FIG. 3C, the hangup frequency 2f1 at the outer track Tout is equal to the hangup frequency 2f1 at the inner track Tin. Hence, during acquisition for clock recovery using the read signal in preamble portions of the outer track Tout, hangup occurs at the point at which the frequency is 2f1, in which case normal clock recovery becomes impossible.
The reason why this hangup occurs is because in conventional Equation 1 for detection of the phase difference Zn, even though the sampled read signals Yn and Yn-1 are both at the level .+-.1, the phase difference Zn appears to be eliminated.
In an effort to solve this problem, the inventor of the present invention has paid attention to a fact that in a zone-bit-recording type magnetic disk drive, the read signal waveform of the training signal which is recorded in the preamble portion of the data is a sinusoidal waveform. The inventor of the present invention has found that the clock signal can be extracted as a continuous signal having an analog waveform without performing sampling from the read signal waveform of the training signal, thus arriving at the present invention.